single pulse generator

上一篇 / 下一篇  2018-12-10 12:41:30 / 個人分類:FSM

最近看了看 FSM based Digital Design using Verilog HDL, 根據Frame. 1.11的狀態轉移圖寫了一個module;

module one_pulse(//input
clk,s,rst_n,
//output
P,L);
input s;
input clk;
input rst_n;
output  P;
output  L;
reg [1:0] state;
reg [1:0] next_state;

//
always @(*) begin
    case(state)
        2'b00: begin
            if (s) begin
                next_state = 2'b10;
            end
            else begin
                next_state = 2'b00;
            end
        end
        2'b10: begin
            next_state = 2'b01; // clk sensitive
            end
        2'b01: begin
            if(!s) begin
                next_state = 2'b00;
            end
            else begin
                next_state = 2'b01;
            end
        end
        default: begin
                next_state =2'b00;
            end
            endcase
end
    always @(posedge clk or negedge rst_n) begin
        if (~rst_n) begin
            state <= 2'b00;
        end
        else begin
            state <= next_state;
        end
end   
assign P = state[1]&~state[0];
assign L = state[1]^state[0];
endmodule

// testbench


module tb ();
reg clk;
reg rstn;
//reg seed;
reg enable;
initial begin
          clk = 0;
          rstn = 1;
          enable = 0;
    #10  rstn = 0;
    #10  rstn = 1;
 
    @(posedge clk) enable = 1;
    @(posedge clk);
    @(posedge clk) enable = 0;
    @(posedge clk);
    @(posedge clk);
    @(posedge clk) enable = 1;
    @(posedge clk) enable = 0;
    @(posedge clk);
    @(posedge clk);
    @(posedge clk) enable = 1;
    @(posedge clk) enable = 0;
    @(posedge clk) enable = 1;  
    #150 $finish;
end
always #5 clk = ~clk;

one_pulse u_one_pulse (//input
.clk(clk),
.s(enable),
.rst_n(rstn),
//output
.P(),
.L());
// wire gclk_and = enable & clk;
endmodule


來自書中的狀態轉移圖:


P: s 拉高后產生一個單脈沖;

有一處存疑就是如果s拉高一個cycle后立即拉低一個cycle, 然后再拉高;行為就會跟預想的不一樣。
這里隱含著一個條件是,兩次s 拉高要大于兩個cycle

multiple pulse generation with resume pin added

module one_pulse_r(//input
clk,s,r,rst_n,
//output
P,L);
input s;
input r;
input clk;
input rst_n;
output  P;
output  L;
reg [1:0] state;
reg [1:0] next_state;
parameter S0 = 2'b00;
parameter S1 = 2'b10;
parameter S2 = 2'b11;
parameter S3 = 2'b01;
//
always @(*) begin
    case(state)
        S0: begin
            if (s) begin
                next_state = S1;
            end
            else begin
                next_state = S0;
            end
        end
        S1: begin
            next_state = S2; // clk sensitive
            end
        S2: begin
            if(r) begin
                next_state = S1;
            end
            else begin
                next_state = S3;
            end
        end
        S3: begin
            if (s) begin
                next_state = S3;
            end
            else begin
                next_state = S0;
            end           
        end
        default: begin
                next_state =S0;
            end
            endcase
end
    always @(posedge clk or negedge rst_n) begin
        if (~rst_n) begin
            state <= 2'b00;
        end
        else begin
            state <= next_state;
        end
end   
assign P = state[1]&~state[0];
assign L = state[1]^state[0];
endmodule


//testbench

    @(posedge clk) enable = 0;
    @(negedge clk) rstn_r = 1;
   
    @(posedge clk) enable = 1;
    // @(posedge clk);
    @(posedge clk) resume = 1;
    @(posedge clk) enable = 0;
    @(posedge clk);
    @(posedge clk);   
    @(posedge clk) resume = 0;

 

// waveform
https://img-blog.csdnimg.cn/20181210170930655.png
resume

// 狀態轉移圖



TAG: fsm FSM

 

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